Rohan makes compilers better 🛠️🚀
Database & Compiler architect | BLAS | HTAP | C++ | FPGAs and other cool electronic circuits
@yosyshq.com
The home for the team maintaining Yosys and related Open Source EDA projects. https://www.yosyshq.com/ Sign up to our newsletter! https://yosyshq.com/newsletter
@rebelmike.bsky.social
Electronics tinkerer, narrowboater, puzzle hunter, board gamer and occasional geocacher. Also on fedi @mike@rebel-lion.uk
@keithjkraus.bsky.social
Co-Founder @VoltronData, @condaforge.bsky.social core. Previously @NVIDIA @RAPIDSAI. My thoughts are my own.
@nihil2501.bsky.social
@aksharvastarpara.bsky.social
@newsycombinator.bsky.social
not affiliated with Y Combinator, running on a pi in my basement
@pipelinec.bsky.social
PipelineC Hardware Description Language An easy to understand hardware description language with a powerful autopipelining compiler and growing set of real life design inspired features. github.com/JulianKemmerer/PipelineC https://discord.gg/Aupm3DDrK2
@gregdavill.bsky.social
ASIC/FPGA/PCB/FW engineer at ASTC 🧙♂️ (He/Him) I also take macro photos of electronics
@dcdietrich.bsky.social
Master of Science in Advanced Software Engineering with Distinction, University of Leicester alumnus, Manager Software Development ICS at Phoenix Contact
@fpga.org
Kilocore RISC-V FPGA accelerators; former Microsoft dev tools architect; Vice-chair RISC-V SoftCPU SIG & Composable Custom Extensions Task Group; blog: https://fpga.org. Cyclist. Let's try kindness. 🇨🇦-🇺🇸
@mattvenn.net
Engineer and Technology Communication. On a mission to make ASICs more accessible. YosysHQ & Tiny Tapeout founder member. https://ZeroToASICcourse.com https://TinyTapeout.com
@piveral.bsky.social
Site: https://piveral.com/ Help guides on Nvidia jetson boards: https://nvidia-jetson.piveral.com/ DM for removal/collab.
@bsky.app
official Bluesky account (check username👆) Bugs, feature requests, feedback: support@bsky.app